library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipeexe is
	generic
	(
		DATA_WIDTH	: natural  :=	32;
		ALUC_WIDTH	: natural  :=	5
	);


	port
	(
		-- Input ports
		-- from pipedereg
		ealuc : in std_logic_vector(ALUC_WIDTH-1 downto 0);
		ealuimm : in std_logic;
		ea : in std_logic_vector(DATA_WIDTH-1 downto 0);
		eb : in std_logic_vector(DATA_WIDTH-1 downto 0);
		eimm : in std_logic_vector(DATA_WIDTH-1 downto 0);
		eshift : in std_logic;

		-- Output ports
		ealu :out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end pipeexe;

architecture rtl_pipeexe of pipeexe is
component alu
	port
	(
		-- Input ports
		aluc	: in  std_logic_vector(4 downto 0);
		a	: in  std_logic_vector(DATA_WIDTH-1 downto 0);
		b   : in  std_logic_vector(DATA_WIDTH-1 downto 0);

		-- Output ports
		--zero	: out std_logic;
		result	: out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end component;
component lpm_mux32
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		sel		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
signal a,b : std_logic_vector(DATA_WIDTH-1 downto 0);
signal sa : std_logic_vector(DATA_WIDTH-1 downto 0) := X"00000000";
begin
	sa(4 downto 0) <= eimm(10 downto 6);
	mux_a: lpm_mux32 port map(
		data0x => ea,
		data1x => sa,
		sel => eshift,
		result => a
	);
	mux_b: lpm_mux32 port map(
		data0x => eb,
		data1x => eimm,
		sel => ealuimm,
		result => b
	);
	alu32: alu port map(
		aluc => ealuc,
		a => a,
		b => b,
		result => ealu
	);
end rtl_pipeexe;

